1. Field of the Invention
The present invention relates to a device for managing writing or reading with respect to a cache memory and a main memory.
2. Description of the Related Art
Conventionally, a management function of a NAND Flash™ memory is built into a file system.
A micro processing unit (MPU) is provided with a cache memory. A dynamic random access memory (DRAM) is used as a main memory. When the MPU accesses the NAND Flash™ memory, an operation is carried out according to the following memory hierarchy in the conventional case.
First, the MPU converts a logical address to a physical address using a memory management unit (MMU) to make an access to a cache memory.
In this case, the MPU accesses the main memory, that is, DRAM, with respect to partial data by virtual memory management of an operating system (OS).
If the MPU further has a need to access the NAND Flash™ memory, the MPU makes the following controls to determine a physical location of the NAND Flash™ memory by a Flash File System. One is a control for avoiding a defective block in NAND Flash™ memory. Another is a control for making accesses to all blocks of the NAND Flash™ memory almost equally (without difference).
The MPU accesses the NAND Flash™ memory based on the determined physical location.
The conventional MPU must execute many operations included in different hierarchy when the number of memory hierarchy is much. For this reason, it is difficult to effect optimization between different hierarchy operations. For example, the MPU makes a changeover of data of the cache memory. In this case, it is difficult to realize control of managing bad block peculiar to the NAND Flash™ memory because the control belongs to different operation memory hierarchy.
A patent document 1 (Jpn. Pat. Appln. KOKAI Publication No. 2001-266580) discloses an invention enable different kind of a semiconductor memory device to be connected to a common bus.
The semiconductor memory device disclosed in the patent document 1 includes a random access memory chip and a package having the random access memory chip. The package has a plurality of pins electrically connecting the random access memory chip to an external device. The pins provide a memory function in common to the random access memory chip and an electrically erasable and programmable non-volatile semiconductor memory. The pins are arrayed according to the corresponding pin position of the non-volatile semiconductor memory.